Semiconductor processes for manufacturing integrated circuits often require forming a protective layer, or layers, to, e.g., reduce contamination by mobile ions, prevent unwanted dopant diffusion between different layers, and isolate elements of an integrated circuit. Typically, such a protective layer is formed with silicon-based dielectrics, such as silicon dioxide, which may take the form of undoped silicate glass (USG), borosilicate glass (BSG), or borophosphorous silicate glass (BPSG). BSG is typically formed by doping USG with Boron. Likewise, BPSG is typically formed by doping USG with both Boron and Phosphorous. If these dielectrics are disposed beneath the first metal layer of the integrated circuit, they are often referred to as pre-metal dielectrics (PMD).
A conventional PMD stack often includes a USG layer disposed on a semiconductor substrate, and a BPSG layer disposed on the USG layer. Typically, a BPSG film layer has a number of advantages over a USG layer. For example, a BPSG layer is often a better moisture barrier than a USG layer. Also, the phosphorous ions in a BPSG layer trap mobile sodium (Na) or other ions. This phenomenon is called “gettering,” and it is sometimes used to reduce or eliminate an unwanted shift in a transistor's threshold voltage VT caused by mobile ions trapped in the gate oxide of the transistor. Additionally, the Boron ions decrease the viscous flow temperature of the BPSG layer. This facilitates reflow of the BPSG layer, and thus improves the reflow planarization of the BPSG layer surface and allows for the filling of gaps with fewer voids. A downside of BPSG is that Boron and Phosphorous ions may diffuse from the BPSG into an underlying silicon region such as a silicon substrate. Such diffusion may cause undesirable changes in the doping profile of the silicon region. Therefore, to prevent such diffusion, the PMD stack includes a USG layer beneath the BPSG layer. The USG layer acts as a barrier to such diffusion.
FIG. 1 is a cross-section of a portion of a conventional semiconductor structure 1. The structure 1 has a patterned field-oxide layer 2 that defines active regions 8 in a semiconductor substrate 10. In one embodiment, the field oxide 2 has a thickness between approximately 3 k to 6 k angstroms. A gate structure 12 is disposed over the active region 8, and a layer 14 is disposed over a segment of the field oxide 2. A USG layer 4 having a thickness between approximately 1 k-2 k angstroms is conventionally formed over the surface of the structure 1. A relatively thick BPSG layer 6 having a thickness between approximately 12 k-25 k angstroms is subsequently formed over the USG layer 4. In one embodiment, the thickness of the BPSG layer 6 is at about 18 k angstroms.
Referring to FIG. 2, after the BPSG layer 6 has been formed, the structure 1 is planarized using a conventional chemical mechanical polishing (CMP) process. The CMP process reduces the combined thickness of all layers above the substrate 10, i.e., from the bottom of the field oxide 2 all the way to the top of the BPSG layer 6, to a value yk. In one embodiment, yk is approximately 12 k angstroms. The layer 4 and the polished layer 6 form a PMD stack 17.
Referring to FIG. 3, an optional plasma-enhanced tetraethyl orthosilicate (PE-TEOS) redeposition dielectric layer 16 having a thickness between approximately 2 k-4 k angstroms may be conventionally formed over the polished BPSG layer 6. Therefore, when present, the layer 16 composes part of the PMD stack 17.
As the semiconductor industry increasingly relies on the CMP technique for planarization in today's high-density integrated circuits, drawbacks of the USG/BPSG PMD stack in connection with the CMP technique become more prominent. First, Boron and Phosphorous dopants in the BPSG layer 6 often are not uniformly distributed across and against the depth of the semiconductor wafer. This non-uniform distribution of the boron and/or phosphorous dopants often causes uneven thickness of the BPSG layer 6 even after CMP. Second, forming the BPSG layer 6, which is typically accomplished by a atmospheric pressure chemical vapor deposition (APCVD) process, is often a low-throughput and high maintenance process. As a result, using a relatively thick sacrificial BPSG layer 6 for the PMD 17 is often burdensome for manufacturing today's high-density integrated circuits. Additionally, the BPSG layer 6 often is too soft for a CMP process to adequately smoothen or planarize the surface of the layer 6.